National Physical Laboratory is commencing a project that will position UK avionics, military and instrumentation sectors to adopt the latest high density chip-scale devices while being assured of continued reliability. This project addresses the interconnect challenge that arises from Moore’s Law. The increasing number of gates in the silicon device places increasing pressure on the number of terminations or inputs and outputs (i/o) from the device. As the i/o pad diameter drops below 100um, current densities will exceed 104A/cm2 where mass diffusion effects undermine the structural integrity of the interconnect. The appearance of voids will lead to high resistance and poor fatigue performance. Here NPL plans to investigate the metallurgical systems and look into developing barrier systems that allow the interconnect to carry higher current densities. The system will be modelled and guidelines produced to allow end users to exploit the technology successfully. Knowledge transfer will include the IAG, the SSTC conferences and a scientific paper.
The benefit this project will bring is in providing the metrology to develop packaging solutions that will allow the use of the latest Si devices, and hence enable the manufacture of custom products in high reliability applications. End users will be able to develop and prove the performance of their equipment, which will allow them to maintain the competitiveness of UK industry.
The work proposed here supports the electronics key technology area of electronics design. The project also contributes to the Advanced Materials technology area, in terms of the metrology requirement of improving lifetime prediction and underpins the ITRS road map.
The project has synergy with others, as an example it will feed into the standards work within SEMI, and falls within the projects being developed within Framework7 and the ELFNET programme.